Athlon 64 FX

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Prozessorkern	Sledgehammer Kern

Entwicklungsgeneration	K8

Kernproduktion	FAB 30, Dresden, Deutschland
Test, Montage, Beschriftung	Penang, Malaysia

Kernphoto	Clawhammer Kern

Transistoren	105,9 Millionen
Fertigungstechnik	9 Lagen, CMOS (Complementary Metal-Oxide Semiconductor), SOI (Silicon On Insulator), 6 Layer low-K Dielektrika, Copper Interconnects


Level 1 Daten Cache	64 KiB
	2-Way Associative
	8-Way Bank-Interleave
	2*64 Bit Zugriffe pro Takt, lesen oder schreiben in verschiedenen Banken
	3 Takte Latenz
	ECC Cache Protection (8 KiB)
	40 TLB (Translation Look aside Buffers) Einträge (32* 4k page translations, 8* 2/4 M page translations)

Level 1 Befehls Cache	64 KiB
	2-Way Associative
	128 Bit Lese- und Schreib-Port
	Parity Protection (1 Bit pro 16 Bit)
	40 ITLB (Instruction Translation Look aside Buffers) Einträge (32* 4k page translations, 8* 2/4 M page translations)

Level 2 Cache	256/512/1024 KiB
	16-Way Associative
	Exclusive Architektur
	16 Takte Latenz (+ 3 Takte L1)
	ECC Cache Protection
	128 Bit Anbindung
	512 DTLB (Data Translation Look aside Buffers, 4-Way set-asociative virtual to physical address translation)
	512 ITLB (Instruction Translation Look aside Buffers, 4-Way set-asociative virtual to physical address translation)


Integer Core	12 stufige Pipeline
	3 ALU (Arithmetic Logic Unit)
	3 AGU (Address Generator Unit)
	64 Bit Integer Register
	48 Bit virtueller Adressraum, 40 Bit physikalischer Adressraum
	16 General Purpose Register

Floating Point Core	17 stufige Pipeline
	1*FMUL
	1*FADD
	1*FSTORE

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